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PRELIMINARY
CY28158
Spread Spectrum Timing Solution for Serverworks Chipset
Features
* Maximized EMI suppression using Cypress's spread spectrum technology * Based on Industry Standard CK133 Pinout with all outputs compliant to CK98 specifications * 0.5% downspread outputs deliver up to 10dB lower EMI * 6 skew-controlled copies of CPU output * 6 copies of PCI output (synchronous w/CPU output) * 2 copies of 66 MHz fixed frequency 3.3V clock * 3 copies of 16.67 MHz IOAPIC clock, synchronous to CPU clock * 1 copy of 48 MHz USB output * 2 copies of 14.31818 MHz reference clock * Programmable to 133 or 100 MHz operation * Power management control pins for clock stop and shut down * Available in 56-pin SSOP Table 1. Pin Selectable Frequency SEL133/100# 1 0 CPU0:5 (MHz) 133 100 PCI 33.3 33.3
Key Specifications
Supply Voltages: ......................................VDD33 = 3.3V 5% .................................................................VDD25 = 2.5V 5% CPU Output Jitter: ................................................... .<150 ps CPU Output Skew:.................................................... <175 ps CPU to 3V66 Output Offset: CPU to IOAPIC Output Offset 0.0 to1.5 ns (CPU leads) 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset ................. 0 to 4.0 ns (CPU leads)
Block Diagram
X1 X2 CPU_STOP#
Pin Configuration
XTAL OSC
2 REF0:1
STOP Clock Logic
6 CPU0:5
SPREAD# SEL0 SEL1 SEL133/100#
PLL 1
/2//1.5 STOP Clock Logic 2 3V66_0:1
1 PCI_F STOP Clock Logic 5 PCI1:5
PWRDWN# PCI_STOP#
/2
Power Down Logic
3 /2 IOAPIC0:2
Tristate Logic
GND_REF REF0 REF1 VDD_REF X1 X2 GND_PCI GND_PCI PCI_F VDD_PCI PCI1 PCI2 GND_PCI PCI3 PCI4 VDD_PCI VDD_PCI PCI5 GND_PCI GND_3V66 GND_3V66 VDD_3V66 VDD_3V66 GND_3V66 3V66_0 3V66_1 VDD_3V66 SEL133/100#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDD_IOAPIC IOAPIC2 IOAPIC1 IOAPIC0 GND_IOAPIC VDD_CPU CPU5 CPU4 GND_CPU VDD_CPU CPU3 CPU2 GND_CPU VDD_CPU CPU1 CPU0 GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ
CY28158
PLL2
1 48MHz
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 9
www.SpectraLinear.com
CY28158
Pin Definitions
Name X1
[1]
Pins 5 6 41, 42, 45, 46, 49, 50 11, 12, 14, 15, 18 9 25, 26 53, 54, 55 2, 3 30 36 37 35 34 33 32 28 1 7, 8, 13, 19 20, 21, 24 29 52 40, 44, 48 38 4 10, 16, 17 22, 23, 27 31 56 43, 47, 51 39
Description Reference crystal input Reference crystal feedback CPU clock outputs PCI clock outputs, synchronously running at 33.33 MHz Free running PCI clock 3V66 clock outputs, running at 66.66 MHz IOAPIC clock outputs, running at 16.67 MHz Reference clock outputs, 14.318 MHz 48-MHz USB clock output Active LOW input, disables CPU and 3V66 clocks when asserted Active LOW input, disables PCI clocks when asserted Active LOW input, powers down part when asserted Active LOW input, enables spread spectrum when asserted CPU frequency select input (See Function Table) CPU frequency select input (See Function Table) CPU frequency select input (See Function Table) 3.3V Reference ground 3.3V PCI ground 3.3V 66-MHz (AGP) ground 3.3V 48-MHz (USB) ground 2.5V APIC ground 2.5V CPU ground Analog ground to PLL and Core 3.3V Reference voltage supply 3.3V PCI voltage supply 3.3V 66-MHz (AGP) voltage supply 3.3V 48-MHz (USB) voltage supply 2.5V APIC voltage supply 2.5V CPU voltage supply Analog voltage supply to PLL and Core
X2[1] CPU [0-5] PCI [1-5] PCI_F 3V66 [0-1] IOAPIC [0-2] REF [0-1] 48MHZ CPU_STOP# PCI_STOP# PWR_DWN# SPREAD# SEL1 SEL0 SEL133/100# GND_REF GND_PCI GND_3V66 GND_48MHZ GND_IOAPIC GND_CPU GNDA VDD_REF VDD_PCI VDD_3V66 VDD_48MHZ VDD_IOAPIC VDD_CPU VDDA
Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, "Crystal Oscillator Topics."
Rev 1.0, November 20, 2006
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CY28158
Function Table[2]
SEL133/ 100# 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 SEL1 0 1 0 1 0 1 0 1 SEL0 Hi-Z 100.227[3] 100 100 TCLK/2 N/A 133.33 133.33 CPU (MHz) Hi-Z 66.818[3] 66.67 66.67 TCLK/4 N/A 66.67 66.67 3V66 (MHz) Hi-Z 33.409[3] 33.33 33.33 TCLK/8 N/A 33.33 33.33 PCI (MHz) 48MHZ (MHz) Hi-Z 48.008[3] OFF 48.008[3] TCLK/2 N/A OFF 48.008[3] Hi-Z 14.318[3] 14.318 14.318 TCLK N/A 14.318 14.318 REF (MHz) IOAPIC (MHz) Hi-Z 16.705[3] 16.67 16.67 TCLK/16 N/A 16.67 16.67
Actual Clock Frequency Values
Clock Output CPU CPU 48MHZ Target Frequency (MHz) 100.0 133.33 48.0 Actual Frequency (MHz) 99.126 132.769 48.008 PPM -8740 -4208 167
Clock Enable Configuration
CPU_STOP# X 0 0 1 1 PWR_DWN# 0 1 1 1 1 PCI_STOP# X 0 1 0 1 CPU LOW LOW LOW ON ON 3V66 LOW LOW LOW ON ON PCI LOW LOW ON LOW ON PCI_F LOW ON ON ON ON REF IOAPIC LOW ON ON ON ON OSC. OFF ON ON ON ON VCOs OFF ON ON ON ON
Clock Driver Impedances
Impedance Minimum Buffer Name CPU, IOAPIC 48MHZ, REF PCI, 3V66 VDD Range 2.375V - 2.625V 3.135V - 3.465V 3.135V - 3.465V Buffer Type Type 1 Type 3 Type 5 13.5 20 12 29 40 30 45 60 55 Typical Maximum
Note: 2. TCLK is a test clock driven in on the X1 input in test mode. 3. This selection is defined as "N/A" or "Reserved."
Rev 1.0, November 20, 2006
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CY28158
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage..................................................-0.5 to +7.0V Input Voltage.............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ....-65 C to +150 C Max. Soldering Temperature (10 sec) ....................... +260 C Junction Temperature................................................ +150 C Package Power Dissipation.............................................. 1W Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions[4] Over which Electrical Parameters are Guaranteed
Parameter VDD_REF, VDD_PCI, VDDA, VDD_3V66, VDD_48MHZ VDD_CPU VDD_IOAPIC TA CL Description 3.3V Supply Voltages CPU Supply Voltage IOAPIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPU, 48MHZ, REF, IOAPIC PCI, 3V66 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.375 2.375 0 Max. 3.465 2.625 2.625 70 20 30 14.318 MHz Unit V V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VOH VOL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input High Current Input Low Current High-level Output Current Except Crystal Pads CPU, IOAPIC 48 MHZ, REF, PCI, 3V66 CPU, IOAPIC 48 MHZ, REF, PCI, 3V66 0 < VIN < VDD 0 < VIN < VDD CPU IOAPIC 48 MHZ, REF 3V66, PCI IOL Low-level Output Current CPU IOAPIC 48 MHZ, REF 3V66, PCI IOZ IDD2 Output Leakage Current 2.5V Power Supply Current Three-state VDDA/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz VOH = 2.0V VOH = 2.0V VOH = 2.4V VOH = 2.4V VOL = 0.4V VOL = 0.4V VOL = 0.4V VOL = 0.4V -16 -60 -20 -72 -15 -51 -30 -100 19 49 25 58 10 24 20 49 10 90 A mA mA IOH = -1 mA IOH = -1 mA IOL = 1 mA IOL = 1 mA 2.0 2.4 0.4 0.4 10 10 A A mA V Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 V V V
Rev 1.0, November 20, 2006
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CY28158
Electrical Characteristics Over the Operating Range (continued)
Parameter IDD3 IDDPD2 IDDPD3 Description 3.3V Power Supply Current 2.5V Shutdown Current 3.3V Shutdown Current Test Conditions VDDA/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz VDDA/VDD33 = 3.465V, VDD25 = 2.625V VDDA/VDD33 = 3.465V, VDD25 = 2.625V Min. Max. Unit 160 100 200 mA A A
Switching Characteristics[5] Over the Operating Range
Parameter t1 t2 t2 t2 t3 t3 t3 t6 t8 t9 t10 t11 t12 t13 All CPU, IOAPIC 48MHZ, REF PCI, 3V66 CPU, IOAPIC 48MHZ, REF PCI, 3V66 CPU IOAPIC 3V66 PCI CPU, 3V66 3V66, PCI CPU, IOAPIC CPU IOAPIC 48MHZ 3V66 REF CPU, PCI Output Description Output Duty Cycle[6] Rising Edge Rate Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate Falling Edge Rate CPU-CPU Skew IOAPIC-IOAPIC Skew 3V66-3V66 Skew PCI-PCI Skew CPU-3V66 Clock Skew 3V66-PCI Clock Skew CPU-IOAPIC Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Settle Time CPU and PCI clock stabilization from power-up t1A/t1B Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 2.0V and 0.4V Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.25V Measured at 1.25V Measured at 1.5V Measured at 1.5V CPU leads. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks 3V66 leads. Measured at 1.5V CPU leads. Measured at 1.25V With all outputs running 0 0.5 1.5 Test Conditions Min. 45 1.0 0.5 1.0 1.0 0.5 1.0 Max. 55 4.0 2.0 4.0 4.0 2.0 4.0 175 250 250 500 1.5 2.5 4 150 500 500 500 1000 3 Unit % V/ns V/ns V/ns V/ns V/ns V/ns ps ps ps ps ns ns ns ps ps ps ps ps ms
Notes: 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. All parameters specified with loaded outputs. 6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
Rev 1.0, November 20, 2006
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CY28158
Switching Waveforms
Duty Cycle Timing
t1A t1B
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3
CPU-CPU Clock Skew
CPUCLK
CPUCLK t6
IOAPIC-IOAPIC Clock Skew
IOAPIC
IOAPIC t8
3V66 - 3V66 Clock Skew
3V66
3V66 t9
Rev 1.0, November 20, 2006
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CY28158
Switching Waveforms (continued)
PCI-PCI Clock Skew
PCI
PCI t10
CPU - 3V66 Clock Skew
CPU
3V66 t11
3V66 - PCI Clock Skew
3V66
PCI t12
CPU-IOAPIC Clock Skew
CPU t13
IOAPIC
CPU_STOP# Timing
CPU (Internal) PCI (Internal) PCI_F (Free-Running) CPU_STOP# CPU, 3V66 (External)
[7, 8]
Notes: 7. CPU on and CPU off latency is 2 or 3 CPU cycles. 8. CPU_STOP# may be applied asynchronously. It is synchronized internally.
Rev 1.0, November 20, 2006
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CY28158
Switching Waveforms (continued)
PCI_STOP#
CPU (Internal) PCI (Internal) PCI_F
(Free-Running)
PCI_STOP# PCI (External)
PWR_DWN#
CPU (Internal) PCI (Internal) PWR_DWN# CPU (External) PCI (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Test Circuit
VDD_PCI, VDD_3V66, VDD_48MHZ, VDD_REF, VDDA
1, 7, 8, 13, 19, 20, 21, 24, 29, 40, 44, 48, 52 4, 10, 16, 17, 22, 23, 27, 31, 39 CY28158
VDD_CPU, VDD_IOAPIC 43, 47, 51, 56
OUTPUTS CLOAD
Note: Each supply pin must have an individual decoupling capacitor on test circuit at 0.1 F. Note: All capacitors must be placed as close to the pins as is physically possible.
Ordering Information
Ordering Code CY28158PVC CY28158PVCT Lead Free CY28158OXC CY28158OXCT O56 O56 56-Pin SSOP 56-Pin SSOP- Tape and Reel Commercial Commercial Package Name O56 O56 Package Type 56-Pin SSOP 56-Pin SSOP- Tape and Reel Operating Range Commercial Commercial
Rev 1.0, November 20, 2006
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CY28158
Package Diagram
56-Lead Shrunk Small Outline Package O56
51-85062-C
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
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